The semiconductor device is an important element for producing an electronic product. The upgrading of the semiconductor device propels the development of the semiconductor technology and the progress of the semiconductor industry, especially improving the performance of the central processing unit (CPU) and memory. Starting from the end of last century, the chip fabrication process has been developed rapidly, and has entered the technology of less than 32 nm from a micrometer level.
As the feature size of the device entered the level of 45 nm or less, the gate control ability of the conventional planar transistor device is gradually reduced, and characteristics of the device are deteriorated and adversely affected by a short channel effect. In the design of the conventional device, the gate oxide layer has a thickness of several nanometers at most and even less than 1 nm. Such a thin gate oxide layer may cause a serious gate leakage current, so that the performance and reliability of the device are deteriorated, and the power consumption of the device is greatly increased. Meanwhile, if it is desired to reduce the junction depth by means of the process, how to achieve the process is faced with a huge challenge. On the other hand, since many thermal issues may be inevitably experienced during the whole fabrication process of the device, many difficulties may be brought into the fabrication of a shallow junction.
In order to solve a series of problems mentioned above, device designers have proposed a multi-gate device structure, such as a double-gate device, a triple-gate device and a surrounding-gate device to improve the gate control ability of the device. Among these, the surrounding-gate structure has the strongest gate control ability. Since the entire channel is surrounded by the gate, the nanowire structure in the surrounding-gate structure becomes the most potential device structure as the length of the channel is reduced to the nanometer scale. This is because the surrounding-gate structure is beneficial to improve the mobility and reliability of the device. Therefore, the nanowire device has become the most ideal device structure in the case that the feature size of the field effect transistor is reduced to the nanometer scale.
Furthermore, the Moore's Law points out that, the number of transistors included in an integrated circuit is to be doubled every 18 months, and the performance of the integrated circuit is also to be doubled. With the increasingly shrink of the feature size of the semiconductor device, a major factor for restricting the Moore's Law has been changed from the size of the operation region to other aspects such as the area of the source/drain, wirings, etc. In the conventional fabrication process of the nanowire, the source and the drain may occupy very large area, which is equivalent to an area twice larger than that of the effective operation region of the channel under the gate control. Undoubtedly, the above problem has become a very important factor for restricting further increase of the integration degree of the integrated circuit. Thus, how to save the areas and optimize the layout design of the silicon nanowire device have already become a subject in current design of the integrated circuit with high integration density.